Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs

Dynamic reconfiguration is a promising approach to enhance the resource efficiency of FPGAs beyond the current possibilities. One of the main prerequisites for its implementation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time. In this paper we present a new communication macro for Xilinx FPGAs that considers the special requirements of these systems. While most solutions that were presented so far enable basic communication between a low number of hardware modules at fixed positions, our approach implements an infrastructure that allows free placement of hardware modules at run-time. Methodologies like 2D-placement of modules, which were analyzed mainly in theory so far, can now be implemented with currently available FPGAs. A tool-flow is presented, that automatically generates the required homogeneous communication infrastructure for any FPGA of the Xilinx Virtex-E to Virtex-5 family. Performance and area requirements are analyzed based on two typical example implementations of a Wishbone bus.